The present invention relates to the fabrication of semiconductor-based devices. More particularly, the present invention relates to the fabrication of dynamic random access memory (DRAM) integrated circuits, including the trench capacitors therein.
The use of trench capacitors as storage elements in a DRAM circuit is well known. In typical trench capacitors, buried plates which are conductive regions disposed toward the bottom of the trench capacitors, are often employed to connect adjacent trench capacitors together. In the prior art, the buried plate is often formed by a conventional deposition process of a suitable dopant-containing layer, which coats the interior surface of the trench. The deposition process is then followed by a dopant drive in step in which the dopant from the deposited dopant-containing layer is driven into the substrate, thereby creating the conductive region which acts as the buried plate.
To facilitate discussion, FIG. 1 depicts a substrate 102, representing the substrate out of which a trench capacitor may be formed. In the example of FIG. 1 and the figures herein, substrate 102 is consistently assumed to be a p-substrate for ease of discussion although an n-substrate may also be employed to form trench capacitors, as is well known to those skilled in the art. Within substrate 102, there is formed a trench 104, typically by a suitable etching process such as dry etching of which reactive ion etching (RIE) is one example.
After trench 104 is formed in substrate 102, a dopant-containing layer 106 is blanket deposited over substrate 102 and over the interior surface of trench 104. Dopant-containing layer 106 may represent, for example, an oxide layer doped with an n-type dopant (if substrate 102 is a p-substrate) such as an arsenic-doped or phosphorous-doped glass layer. The arsenic-doped layer may include, for example, a nitride/oxide cap layer to avoid outdiffusion annealing. Conversely, if substrate 102 is an n-substrate, dopant-containing layer 106 may include, for example, p-type dopants such as boron. Dopant-containing layer 106 may be deposited using any suitable deposition process including, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).
In FIGS. 2 and 3, a photoresist plug is formed within trench 104 to facilitate etching of a portion of the deposited dopant-containing layer 106. Removal of a portion of the deposited dopant-containing layer 106 is necessary since it is undesirable to have buried plate dopants diffused into the substrate region that is adjacent to the device area (such as the source and/or drain of the DRAM cell's transistor, i.e., the upper region of trench 104). Thus, a photoresist fill step is performed in FIG. 2, which fills trench 104 with a photoresist material (110). In FIG. 3, the photoresist (110) is first etched back to the level shown by reference numeral 112 using a conventional photoresist etch back process. Dopant-containing layer 106 is then etched back to the level of the etched back photoresist (i.e., to about the level indicated by reference numeral 112 in FIG. 3).
In FIG. 4, previously etched back photoresist plug 110A is removed and a cap layer 114 comprising, for example, a three-layer sandwich of oxide/nitride/oxide (ONO) (with one of the oxide layers acting as an adhesion promoting layer between the nitride and the substrate material) or a two-layer nitride/oxide (NO), is deposited into trench 104 and over previously etched back dopant-containing layer 106A. One of the functions of cap layer 114 is to keep the buried plate dopant (e.g., arsenic) from leaving the trench in the subsequently dopant drive in process in which a high temperature step is employed to drive the dopants from dopant-containing layer 106 into the substrate region at the bottom of trench 104.
In FIG. 5, a high temperature dopant drive in process is employed to cause the buried plate dopant material in dopant-containing layer 106 to diffuse into the adjacent substrate region to form the aforementioned conductive region of the buried plate. The dopant drive in process may be accomplished by, for example, exposing the substrate to high temperature for a specified duration (e.g., first for about 1050.degree. C. for about 20 seconds in an Argon or N.sub.2 atmosphere). After the dopant has penetrated a suitable distance into the substrate material to form the buried plate (shown in FIG. 5 as buried plate 116), both cap layer 114 and dopant-containing layer 106 are removed in a subsequent etch process (e.g., a wet etch). It should be noted that FIG. 5 only shows a portion of the buried plate and that a buried plate may be connected to a plurality of trench capacitors. Thereafter, additional conventional processing steps are employed to form other components of the trench capacitor (including the oxide collar in region 120) and the associated DRAM cell.
Although the prior art technique for forming the buried plate has in the past accomplished the task of forming a conductive region at the bottom of the trench, there are significant disadvantages. For example, the prior art process requires the actual deposition of a dopant-containing layer (e.g., dopant-containing layer 106 of FIG. 1). For relatively low-density devices, the trenches have a relatively wide trench opening, and this deposition requirement is typically met without much difficulty. As the density of modern integrated circuits increases, however, the trenches become smaller in cross-section and more closely packed together. Concomitantly, the trench opening is significantly smaller, although the trenches may remain deep to provide sufficient storage capacity to act as storage cells (e.g., 40 FF/DT). By way of example, modern high density DRAMs (e.g., 1 gigabit or above) may require that the trenches be as small as 0.15 micron across and up to 6 microns deep.
The narrow and/or high aspect ratio trenches create additional challenges for process engineers, particularly in the formation of robust layers and structures at the bottom of the narrow, high aspect ratio trenches. In particular, the use of narrow trenches render the deposition process that forms the dopant-containing layer (e.g., dopant-containing layer 106 of FIG. 1) unreliable. It has been discovered that when the trench cross-section decreases below a certain size, voids often form in the dopant-containing layer within the trench, particularly near the bottom of the trench where the buried plate is to be formed. An exemplary void 202 in dopant-containing layer 106 is depicted in FIG. 1.
Further, the deposition of the dopant-containing layer often pinches off the trench opening before the interior of the trench is adequately coated with a layer of dopant-containing material, thereby resulting in dopant deficiency by preventing an adequate amount of dopant-containing material to be present within the trench. The voids and/or dopant deficiency adversely affect the electrical performance of the subsequently formed buried plate since the voids may cause unevenness in the dopant concentration within the buried plate, while the dopant deficiency may result in an inadequate dopant concentration within the buried plate, thereby increasing the impedance of the buried plate. By way of example, buried plate 116 of FIG. 5 shows a defect region 130, which is caused by void 202 of FIG. 1. If sufficiently severe, these defects may render the formed DRAM cell defective.
In view of the foregoing, there are desired improved techniques for forming the DRAM trench capacitor, including the buried plate within the trench.